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g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 1 - features : description : * 65,536 words by 16 bits organization. * fast access time and cycle time. * dual we input. * low power dissipation. * read-modify-write, ras -only refresh, cas -before- ras refresh, hidden refresh and test mode capability. * 256 refresh cycles per 4ms. * available in 40-pin 400 mil soj ,and 40/44 pin tsop(ii). * single 5.0v 10% power supply, except 5v+5% ,-10% for 30ns tsopii package. * all inputs and outputs are ttl compatible. * extended data- out(edo) page mode operation. the glt41216 is a 65,536 x 16 bit high- performance cmos dynamic random access memory. the glt41216 offers fast page mode with extended data output, and has both byte write and word write access cycles via two we pins. the glt41216 accepts 256-cycle refresh in 4ms interval. all inputs are ttl compatible. edo page mode operation allows random access up to 256 x 16 bits, within a page, with cycle times as short as 12ns. the glt41216 is best suited for graphics, and dsp applications requiring high performance memories. high performance 30 35 40 45 max. ras access time, ( t rac ) 30 ns 35 ns 40 ns 45 ns max. column address access time, ( t aa ) 15 ns 18 ns 20 ns 22 ns min. extended data out page mode cycle time, ( t pc ) 12 ns 13 ns 15 ns 18 ns min. read/write cycle time, ( t rc ) 65 ns 70 ns 75 ns 80 ns max. cas access time ( t cac ) 10 ns 11 ns 12 ns 12 ns
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 2 - pin configuration : pin descriptions: name function a 0 - a 7 address inputs ras row address strobe cas column address strobe uw read/upper byte write enable lw read/lower byte write enable oe output enable dq 0 - dq 15 data inputs / outputs v cc +5v power supply v ss ground nc no connection glt41216 soj top view tsop(type ii) top view
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 3 - absolute maximum ratings* capacitance* t a =25 c, v cc =5v 10%, v ss =0v operating temperature, t a (ambient) .......................................-0 c to +70 c storage temperature(plastic)....-55 c to +150 c voltage relative to v ss . ..............-1.0v to + 7.0v short circuit output current......................50ma power dissipation ......................................1.0w symbol c in1 c in2 c out param eter address input ras , cas , uw , lw , oe data input/ output max. 5 7 7 unit pf pf pf *note: operation above absolute maximum ratings can adversely affect device reliability. *note: capacitance is sampled and not 100% tested electrical specifications l we means uw and lw . l all voltages are referenced to gnd. l after power up, wait more than 100 m s and then, execute eight cas -before- ras or ras -only refresh cycles as dummy cycles to initialize internal circuit. block diagram :
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 4 - extended data output (edo) page mode the edo page mode is a kind of page mode with enhanced features. the two major features of the edo page mode are as follows. 1. data output time is extended. in the edo page mode, the output data is held to the next cas cycle?s falling edge, instead of the rising edge. for this reason, valid data output time in the edo page mode is extended compared with the fast page mode (=data extend function). in the fast page mode, the data output time becomes shorter as the cas cycle time becomes shorter. therefore, in the edo page mode, the timing margin in read cycle is larger than of the fast page mode even if the cas cycle time becomes shorter. 2. the cas cycle time in the edo page mode is shorter than that in the fast page mode. in the edo page mode, due to the data extend function, the cas cycle time can be shorter than in the fast page mode if the timing margin is the same. taking a device whose t rac is 60ns as an example, the cas cycle time in the edo page mode is 25ns while that in the fast page mode is 40ns. in the edo page mode, read (data out) and write (data in) cycles can be executed repeatedly during one ras cycle. the edo page mode allows both read and write operations during one cycle, but the performance is equivalent to that of the fast page mode in that case.
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 5 - truth table: glt41216 function ras cas uw lw oe address dqs note s standby h h ? x x x x high-z read: word l l h h l row/col data out write: word(early write) l l l l x row/col data-in write: lower byte (early) l l h l x row/col lower byte,data-in upper byte,high-z write: upper byte (early) l l l h x row/col lower byte,high-z upper byte,data-in read write l l h ? l h ? l l ? h row/col data- out,data-in 1,2 edo-page- 1st cycle l h ? l h h l row/col data-out 1 mode read 2nd cycle l h ? l h h l col data-out 1 edo-page- 1st cycle l h ? l l l x row/col data-in 2 mode write 2nd cycle l h ? l l l x col data-in 2 edo-page- 1st cycle l h ? l h ? l h ? l l ? h row/col data- out,data-in 1,2 mode read- write 2st cycle l h ? l h ? l h ? l l ? h col data- out,data-in 1,2 hidden read l ? h ? l l h h l row/col data-out 1 refresh write l ? h ? l l l l x row/col data-in 2,3 ras -only refresh l h x x x row high-z cbr refresh h ? l l x x x high-z notes: 1. these read cycles are always word read cycles. 2. these write cycles may also be byte read cycles (either uw or lw active). 3. early write only.
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 6 - dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc =5v 10%, v ss =0v, unless otherwise specified. sym. parameter test conditions access time min. typ max. unit notes i li input leakage current (any input pin) 0v v in 5.5v (all other pins not under test=0v) -10 +10 m a i lo output leakage current (for high-z state) 0v v out 5.5v output is disabled ( hiz) -10 +10 m a i c c1 operating current, random read/write t rc = t rc (min.) t rac = 30ns t rac = 35ns t rac = 40ns t rac = 45ns 180 170 160 150 ma 1,2 i cc2 standby current,(ttl) ras , cas , at v ih other inputs 3 v ss 2 ma i cc3 refresh current, ras -only ras cycling, cas , at v ih t rc = t rc (min.) t rac = 30ns t rac = 35ns t rac = 40ns t rac = 45ns 180 170 160 150 ma 2 i cc4 operating current, edo page mode ras at v i l , cas address cycling: t pc = t pc (min.) t rac = 30ns t rac = 35ns t rac = 40ns t rac = 45ns 180 170 160 150 ma 1,2 i cc5 refresh current, cas before ras ras , cas , address cycling: t rc = t rc (min.) t rac = 30ns t rac = 35ns t rac = 40ns t rac = 45ns 180 170 160 150 ma 1 i cc6 standby current, (cmos) ras 3 v cc -0.2v, cas 3 v cc -0.2v, all other inputs v ss 1 ma v il input low voltage -1 +0.8 v 3 v ih input high voltage 2.4 v cc +1 v 3 v ol output low voltage i ol = 4.2ma 0.4 v v oh output high voltage i oh = -5ma 2.4 v notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc (max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions specified i cc (max.) is measured with a maximum of one transition per address cycle in random read/write and edo fast page mode. 3.specified v il (min.) is steady state operation. during transitions v il (min.) may undershoot to -1.0v for a period not to exceed 20ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v cc .
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 7 - ac characteristics t a = 0 c to 70 c , v cc = 5 v 10 % , vih/vil = 2.4/0.8 v, v oh /v ol = 2.0/0.8v an initial pause of 100 m s and 8 cas -before- ras or ras -only refresh cycles are required after power-up. 30 35 40 45 parameter symbol min. max. min. max. min . max. min . max. unit notes read or write cycle time t rc 65 70 75 80 ns read modify write cycle time t rwc 85 87 93 103 ns ras precharge time t rp 25 25 25 30 ns ras pulse width t ras 30 100k 35 100k 40 100k 45 100k ns access time from ras t rac 30 35 40 45 ns 1,2,3 access time from cas t cac 10 11 12 12 ns 1,5,10 access time from column address t aa 15 18 20 22 ns 1,5,6 cas to output low-z t clz 0 0 0 0 ns cas to output high-z t cez 3 3 8 3 8 3 8 ns ras hold time t rsh 10 12 12 13 ns ras hold time referenced to oe t roh 7 8 8 9 ns cas hold time t csh 25 30 34 40 ns cas pulse width t cas 4.5 6 10k 6 10k 7 10k ns ras to cas delay time t rcd 13 17 24 18 28 18 33 ns ras to column address delay time t rad 10 12 17 13 20 13 23 ns 7 cas to ras precharge time t crp 5 5 5 5 ns row address set-up time t asr 0 0 0 0 ns row address hold time t rah 6 7 8 8 ns column address set-up time t asc 0 0 0 0 ns column address hold time t cah 6 6 6 6 ns column address to ras lead time t ral 15 18 20 23 ns column address hold time referenced to ras t ar 26 30 34 39 ns read command set-up time t rcs 0 0 0 0 ns read command hold time referenced to cas t rch 0 0 0 0 ns 4 read command hold time referenced to ras t rrh 0 0 0 0 ns 4 write command set-up time t wcs 0 0 0 0 ns 8,9 write command hold time t wch 6 6 6 6 ns write command pulse width t wp 6 6 6 6 ns
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 8 - ac characteristics 30 35 40 45 parameter symbol min. max. min. max. min. max. min . max. unit notes write command to ras lead time t rwl 10 11 12 12 ns write command to cas lead time t cwl 10 11 12 12 ns data set-up time t ds 0 0 0 0 ns data hold time t dh 6 7 8 8 ns data hold time referenced to ras t dhr 26 31 36 41 ns ras to we delay time t rwd 44 49 54 59 ns cas to we delay time t cwd 22 23 24 24 ns column address to we delay time t awd 25 30 32 34 ns ras to cas precharge time t rpc 0 0 0 0 ns access time from cas precharge t cpa 17 20 22 24 ns edo page mode cycle time t pc 12 13 15 18 ns edo page mode read-modify-write cycle time t prwc 43 47 50 52 ns cas precharge time (edo page mode) t cp 4.5 5 5 7 ns ras pulse width (edo page mode only) t rasp 30 100k 35 100k 40 100k 45 100k ns access time from oe t oea 10 11 12 12 ns oe to data delay time t oed 8 8 8 8 ns oe to output high-z t oez 3 8 3 8 3 8 3 8 ns oe command hold time t oeh 6 6 7 7 ns data output hold after cas low t doh 3 3 3 5 ns ras to output high-z t rez 3 8 3 8 3 8 3 8 ns we to output high-z t wez 3 10 3 10 3 10 3 10 ns oe to cas hold time t och 8 8 8 8 ns cas hold time to oe t cho 8 8 8 8 ns oe precharge time t oep 8 8 8 8 ns cas set-up time for cas -before- ras cycle t csr 10 10 10 10 ns cas hold time for cas -before- ras cycle t chr 10 10 10 10 ns transition time t t 1.5 50 2 50 2 50 2 50 ns refresh period t ref 4 4 4 4 ms
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 9 - notes: 1. measure with a load equivalent to 1ttl inputs and 50 pf. 2. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), access time will be t aa dominant. 3. assumes that t rad t rad (max.). if t rad is greater than t rcd (max.), access time will be controlled by t cac . 4. either t rrh or t rch must be satisfied for a read cycle. 5. access time is determined by the longest of t aa , t cac and t cpa . 6. assumes that t rad 3 t rad (max.). 7. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t aa and t cac . 8. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 9. t wcs (min.) must be satisfied in an early write cycle. 10. t ds and t dh are referenced to the latter occurrence of cas or we . 11. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 2 ns.
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 10 - read cycle row address column address data-out t rc t ras t rp t crp t csh t rcd t rsh t cas t crp t asr t rah t rad t asc t cah t ral t rch t rrh t ar t rcs t aa t oea t cez t oez t cac t clz t rac don't care v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v oh- v ol- dq early write cycle note : d out = open t rp t rc t crp t csh t crp t rcd t rsh t cas t asr t rah t rad t asc t cah t ral t cwl t rwl t wcr t wch t wp t wcs t ar t ds t dh t dhr data - in column address row address v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v ih- v il- dq don't care t ras
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 11 - oe controlled write cycle note : d out = open t rp t rc t crp t csh t crp t rcd t rsh t cas t asr t rah t rad t asc t cah t ral data - in column address row address v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v ih- v il- dq don't care t ras t rcs t cwl t rwl t wp t ds t oed t oeh t dh read - modify - write cycle t rp t rc t crp t crp t rcd t rsh valid data-out column address row addr. v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v i/oh- v i/ol- dq don't care t ras valid data-in t cas t asr t rah t rad t asc t cah t csh t awd t cwd t rwl t cwl t wp t oea t clz t cac t aa t rac t dh t ds t oed t oez
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 12 - edo page mode read cycle note : d out = open t rasp t rp t crp t rcd t cas t csh t cp t cas t cas t cas t cp t cp t pc t pc t pc t csr t rah t rad t asc t asc t asc t asc t cah t cah t cah t cah t rcs t rch t rrh t oea t oea t cac t cpa t aa t och t cpa t aa t cac t oep t cho t aa t cac t cpa t clz t olz t rac t cac t doh t oez t oep t oez t oez valid data-out valid data-out valid data-out valid data-out valid data-out v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe dq v oh- v ol- row addr. column address column address col. addr. col. addr. don't care t rhcp edo page mode early write cycle note : d out = open t rasp t rp t crp t rcd t cas v ih- v il- ras v ih- v il- cas t cas t cas t cp t cp t pc t pc t rsh t asr t rad t rah t asc t cah t csh t asc t asc t cah t cah t wcs t wp t wch t wcs t wcs t wch t wch t wp t wp t ds t ds t ds t dh t ds t ds v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row addr. column address column address column address valid data-in valid data-in valid data-in don't care t rhcp
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 13 - edo page mode read - modify - write cycle note : d out = open t rasp t rp v ih- v il- ras v ih- v il- cas don't care t csh t rcd t cas t cp t cas t rsh t crp t rad t rah t asr t asc t cah t asc t cah t ral t prwc t rcs t wp t cwl t wp t cwl t rwl t cwd t awd t rwd t oea t cwd t awd t cpwd t oea t oeh t rac t aa t cac t oez t oed t ds t dh t aa t cac t oez t oed t ds t dh t clz t clz valid data-out valid data-in valid data-out valid data-in row addr. col. addr. col. addr. v ih- v il- address v ih- v il- we v ih- v il- oe v i/oh- v i/ol- dq edo page read and write mixed ccycle t rasp t rp t cas t hpc t cas t cas t cp t cp t cp t asr t hpc t hpc t rah t asc t cah t asc t asc t asc t cah t cah t cah t rcs t rch t rcs t rch t rch t wcs t wch t wpe t cpa t clz t wed t wez t rac t aa t cac t oea t wez t ds t dh t aa t rez valid data-out valid data-out valid data-out valid data-in row addr col. addr column address column address column address v ih- v il- v ih- v il- v ih- v il- v ih- v il- v ih- v il- v i/oh- v i/ol- ras cas address we oe dq 0 ~ dq 3 don't care
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 14 - cas - before - ras refresh cycle v ih- v il- ras t ras t ras t rp t rp t rc t rc t csr t csr t chr t chr t rpc t rpc t crp v ih- v il- cas t wrh t wrp v ih- v il- we t wrp t wrh remark address , oe : don?t care dq : hi - z ras -only refresh cycle v ih- v il- ras t ras t ras t rp t rp t rc t rc t rpc t crp v ih- v il- cas t crp t asr t asr t rah t rah row address row address address v ih- v il- remark we, oe : don?t care dq : hi - z hidden refresh cycle ( read ) t rp t crp t rcd v ih- v il- ras v ih- v il- cas t rac v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row address don't care t rp t cac t rcs t asc t cah t asr t cah t rad t ral t rsh t chr t rc t ras t ras column address t rc t wrh t aa t oea t clz t rez t cez t wez t oez data-out open t wrp t rrh
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 15 - hidden refresh cycle ( write ) note : d out = open t rp t crp t rcd v ih- v il- ras v ih- v il- cas t ds v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row address don't care t rp t dh t wp t wch t wcs t asc t cah t asc t cah t rad t rsh t rsh t chr t rc t ras t ras column address data-in t wrp t wrh
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 16 - cas-before ras refresh counter test cycle t cas t cpt v ih- v il- ras v ih- v il- cas t rp t ras t csr t chr t rsh t ral t asc t aa t cac t rcs t rrh t rch t wrp t wrh t wrh t wrp t oea t cez t oez t clz t rwl t cwl t wch t wcs t wp t ds t dh t rcs t awd t cwd t rwl t cwl t wp t dh t ds t oed t oez t clz t cac t aa t oea open column address valid data-out valid data-in don't care valid data-in valid data-out v ih- v il- address v ih- v il- we v ih- v il- oe v oh- v ol- dq v ih- v il- we v ih- v il- oe v ih- v il- dq v ih- v il- we v ih- v il- oe v i/oh- v i/ol- dq read cycle write cycle read-modify-write t cah t wrp t wrh
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 17 - ordering information part number speed power feature package GLT41216-30J4 30ns normal edo soj 400mil 40l glt41216-35j4 35ns normal edo soj 400mil 40l glt41216-40j4 40ns normal edo soj 400mil 40l glt41216-45j4 45ns normal edo soj 400mil 40l glt41216-30tc 30ns normal edo tsop 400mil 44l glt41216-35tc 35ns normal edo tsop 400mil 44l glt41216-40tc 40ns normal edo tsop 400mil 44l glt41216-45tc 45ns normal edo tsop 400mil 44l parts numbers (top mark) definition : glt 4 12 16 - 30 j4 note : c cdrom , h hdd. example : 1.glt710008- 15t 1mbit(128kx8)15ns 5v sram pdip(300mil)package type. 2.glt44016- 40j4 4mbit(256kx16)40ns 5v dram soj(400mil)package type. 4 : dram 6 : standard sram 7 : cache sram 8 : synchronous burst sram -sram 064 : 8k 256 : 256k 512 : 512k 100 : 1m -dram 10 : 1m(c/edo)* 11 : 1m(c/fpm)* 12 : 1m(h/edo)* 13 : 1m(h/fpm)* 20 : 2m(edo) 21 : 2m(fpm) 40 : 4m(edo) 41 : 4m(fpm) 80 : 8m(edo) 81 : 8m(fpm) *see note voltage blank : 5v l : 3.3v m : mix voltage config. 04 : x04 08 : x08 16 : x16 32 : x32 speed -sram 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -dram 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns package t : pdip(300mil) ts : tsop(type i) tc : tsop(type ll) pl : plcc fa : 300mil sop fb : 330mil sop fc : 445mil sop j3 : 300mil soj j4 : 400mil soj p : pdip(600mil) q : pqfp tq : tqfp
g-link glt41216 64k x 16 cmos dynamic ram with extended data output aug 1999 (rev.2.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 18 - package information 400mil 40 pin small outline j-form package (soj) 40/44 lead thin small outline package tsop(type ii)

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